1. Field of the Invention
The present invention concerns general purpose charge mode analog operation circuit for attaining, on the same hardware, an adder, multiplier, divider (A/D converter) and other functions according to the difference of their operation status.
2. Description of the Prior Art
Recent developments in digital technology have achieved massive and systematic stacks of microscopic structures of extremely simple elements based on cascadic signal processing modes unified by a simple standard referred to as binary logic.
On the other hand, miniaturization and pursuit of higher speed of digital circuits through the development of processing technology tends to increase power consumption giving rise to more serious problems of supplying more power and handling greater heat dissipation.
Analog technology however utilizes the interaction of devices, so that standardization is difficult and developments with respect to miniaturization or introduction higher functions is extremely slow compared with digital technology.
However, systems involved with physical phenomena must always have some portion for handling analog signals, and in many cases depending on the objective, it is more efficient in terms of cost, power consumption and accuracy to process directly an analog signal, rather than use digital technology. However progress is needed towards standardized processing in analog circuits in the future to conquer current problems such as variations in accuracy, drift and circuit size.
The charge transfer device is particularly unique among devices because of its ability to handle a sampled analog signal so as to enable information processing; essentially of the cascade type, and having properties making it ideal for analog circuit standardization along with extremely low power consumption.
Though slightly differing from the topic of analog signal processing, it has been proposed to use a CCD, which is one kind of charge transfer device, as multi-value memory and arrange them in arrays for use in a digital processing system (please refer to: J. HAN; PROGRESS IN COMPUTER-AIDED VLSI DESIGN; VOL.3; IMPLEMENTATIONS; pp.67-118; ABLEX PUBLISHING, 1989 or H. G.KERKHOFF et al.; IEEE trans. on Computers, C-30, No.9; 1981; PP.644-652), however, as a result of abandoning the advantage of charge transfer device of "enabling analog signal processing", the configuration becomes complex and many restrictions are imposed without realizing a sufficient function, so that the CCD has not been widely used in this field.
On the other hand, efforts have been made elsewhere implementing a multiplier using a CCD. As shown in FIG. 13, for example, Chiang et al. have prepared charge input gates of the number corresponding to bit number, manufactured by way of a trial a multiplier wherein multiplication type D/A conversion is performed by adding signals in the charge domain, and confirmed some performance. [Please refer to: (U.S. Pat. No. 4,464,726 CHARGE DOMAIN PARALLEL PROCESSING NETWORK (A. M. CHIANG 1984) or U.S. Pat. No. 5,089,983 CHARGE DOMAIN VECTOR-MATRIX PRODUCT PROCESSING SYSTEM (A. M. CHIANG 1992).]
Now, as shown in FIG. 14, the inventors have proposed a method comprising a multiplication type converter by directly dividing the charge input and selectively accumulating them according to a digital signal bit and, moreover, have proposed an A/D converter of similar composition. [Please refer to: Tokkaihei No.6-237173, "D/A converter or multiplier using charge transfer device", Tokuganhei No. 5-154513, "D/A converter for charge signal", Tokuganhei No. 5-154514, "A device for dividing charge signal into two equal parts", Tokuganhei No. 5-312640, "Systolic array processor", Tokuganhei No. 6-200255, "Multiplier using charge transfer device".]
All these embodiments have a specialized configuration for achieving a single function and do not have flexibility for allowing to a multiplier used as an adder; however among them, the system proposed by the inventors is relatively easy to standardize because of its simple composition.